Automatic semiconductor wafer tester



FIG. 1 is a top and left front perspective view of an automatic semiconductor wafer tester showing my new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a front elevational view thereof;

FIG. 4 is a rear elevational view thereof;

FIG. 5 is a left side elevational view thereof;

FIG. 6 is a right side elevational view thereof. 

The ornamental design for an automatic semiconductor wafer tester, as shown. 